The present invention relates, in general, to optimization of the verification of the validity of automated test procedures, and more particularly to electrical function and timing tests of application specific integrated circuit parts (ASIC parts).
Electrical testing of ASIC parts utilizes complex and expensive automated test equipment, special purpose machines designed to apply a set of input stimuli to an ASIC part and to compare the resultant set of output states with a set of expected output states. The set of stimuli and expected output state for each time step is unique to each design of an ASIC part. The set of stimuli and expected output states to be used for a given design is typically generated by use of event based digital simulation software such as LASAR (trademark of Teradyne, Inc.), Verilog (trademark of Cadence, Inc.), or Quicksim (trademark of Mentor Graphics, Inc.). This software accurately simulates the internal functioning and timing of the ASIC part, creating time-based stimulus and expected response information as a combination of timing information and state information.
The timing information can specify a unique timing for each potential state change of each signal within the state based vector if required, but typically only a relatively small amount of timing information is needed. Due to the design of automated test equipment, a single set of timing information is typically applied to a large number of state based vectors at one time and is encoded separately as a uniquely identified timing statement. Timing information is typically defined as being relative to a master clock signal, the leading edge of the clock pulse is typically used for a timing reference. This reference is used internally by the test equipment to accurately trigger the application of signals to the pins of the ASIC device or to enable sensors for output signals.
Timing constraints are placed on the state based vector information and timing information due to the internal design of the ASIC part as well as limitations of the test equipment. Timing constraint information typically consists of a Set of times when a given signal must remain in a stable state relative to another signal and is derived by a static timing analysis of each ASIC part. Static timing analysis is a procedure whereby the internal logic paths of an ASIC part are traced to determine the internal logic path delays from each input to each time critical functional block such as a flip-flop. This internal logic path delay information is used to derive a set of timing restriction rules for each input of the ASIC part. The set of timing restriction rules specify the times at which a signal applied to each input must remain stable relative to another signal for the ASIC part to operate correctly. In order to assure that the part is being tested with a valid stimulus set, both the state information must be verified and the timing restriction rules must be compared with the time-based stimulus information to ensure that no constraints are violated during the testing procedure.
The prior art method is to process the mixed stimulus information for each vector of the mixed time and state based vector information; identify the times when a state transition is not allowed from the timing constraint information; then check for state changes in the state-based stimulus information during those times. This method is straightforward and thorough, but performs a great many unnecessary checks. A typical ASIC part will have more than 10,000 vectors and some ASIC parts have 500,000 or more. So any reduction in the number of verification steps required is highly desirable. In addition, it is highly desirable to allow different automated test equipment to be selected immediately before the tests are performed rather than some weeks earlier during the design activity.